PIC10(L)F320/322
TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
INTCON
GIE
PEIE TMR0IE INTE
IOCIE TMR0IF INTF
IOCIF
40
IOCAF
—
—
—
—
IOCAF3 IOCAF2 IOCAF1 IOCAF0
76
IOCAN
—
—
—
—
IOCAN3 IOCAN2 IOCAN1 IOCAN0
75
IOCAP
—
—
—
—
IOCAP3 IOCAP2 IOCAP1 IOCAP0
75
OPTION_REG WPUEN INTEDG T0CS T0SE
PSA
PS<2:0>
95
PIE1
—
ADIE
—
NCO1IE CLC1IE
—
TMR2IE
—
41
PIR1
—
ADIF
—
NCO1IF CLC1IF
—
TMR2IF
—
42
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupts.
2011-2015 Microchip Technology Inc.
DS40001585D-page 43