PIC12F1840 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC12F1840' PDF : 410 Pages View PDF
PIC12(L)F1840
9.3 Register Definitions: Voltage Regulator Control
REGISTER 9-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)
U-0
—
bit 7
U-0
U-0
U-0
U-0
U-0
R/W-0/0
—
—
—
—
—
VREGPM
R/W-1/1
Reserved
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
bit 1
bit 0
Unimplemented: Read as ‘0’
VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep(2)
Draws lowest current in Sleep, slower wake-up
0 = Normal-Power mode enabled in Sleep(2)
Draws higher current in Sleep, faster wake-up
Reserved: Read as ‘1’. Maintain this bit set.
Note 1: PIC12F1840 only.
2: See Section 30.0 “Electrical Specifications”.
TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE TMR0IF
INTF
IOCAF
—
—
IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1
IOCAN
—
—
IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1
IOCAP
—
—
IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSP1IE CCP1IE TMR2IE
PIE2
OSFIE
—
C1IE
EEIE
BCL1IE
—
—
PIR1
TMR1GIF ADIF
RCIF
TXIF
SSP1IF CCP1IF TMR2IF
PIR2
OSFIF
—
C1IF
EEIF
BCL1IF
—
—
STATUS
—
—
—
TO
PD
Z
DC
VREGCON(1)
—
—
—
—
—
—
VREGPM
WDTCON
—
—
WDTPS<4:0>
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode.
Note 1: PIC12F1840 only.
IOCIF
IOCAF0
IOCAN0
IOCAP0
TMR1IE
—
TMR1IF
—
C
Reserved
SWDTEN
Register
on Page
74
111
111
111
75
76
77
78
16
82
85
DS41441C-page 82
2011-2012 Microchip Technology Inc.
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