PIC14000T-20I/SP View Datasheet(PDF) - Microchip Technology
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MFG CO.
'PIC14000T-20I/SP' PDF : 153 Pages View PDF
PIC14000
4.2.2.5 PIR1 REGISTER
This register contains the individual flag bits for the
Peripheral interrupts (Figure 4-7).
Note:
These bits will be set by the specified
condition, even if the corresponding
Interrupt Enable bit is cleared (interrupt
disabled) or the GIE bit is cleared (all
interrupts disabled). Before enabling an
interrupt, the user may wish to clear the
corresponding interrupt flag, to ensure that
the program does not immediately branch
to the Peripheral Interrupt service routine.
FIGURE 4-7: PIR1 REGISTER
R/W
CMIF
bit7
R R R/W R/W R/W
— — PBIF I2CIF RCIF
R/W
ADCIF
R/W
OVFIF
bit0
Register: PIR1
Address: 0Ch
POR value: 00h
W: Writable
R: Readable
U: Unimplemented,
read as ‘0’
OVFIF: A/D counter Overflow Interrupt Flag
1 = An A/D counter overflow has occurred.
Must be cleared in software.
0 = An A/D counter overflow has not occurred
ADCIF: A/D Capture Interrupt Flag
1 = An A/D capture has occurred.
Must be cleared in software.
0 = An A/D capture has not occurred
RCIF: PORTC Interrupt on Change Flag
1 = At least one RC<7:4> input changed.
Must be cleared in software.
0 =None of the RC<7:4> inputs have changed
I2CIF: I2C Port Interrupt Flag
1 = A transmission/reception is completed.
Must be cleared in software.
0 =Waiting to transmit/receive
PBIF: External Pushbutton Interrupt Flag
1 = The external pushbutton interrupt has occurred
on OSC1/PBTN. Note: This interrupt is not available
in HS mode.
0 =The external pushbutton interrupt did not occur
Unimplemented. Read as ‘0’
Unimplemented. Read as ‘0’
CMIF: Programmable Reference Comparator Interrupt Flag
1 = The comparator output has tripped. This is a
level-sensitive interrupt.
0 = The interrupt did not occur
© 1996 Microchip Technology Inc.
Preliminary
DS40122B-page 21
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