PIC16CR58A-04I/SO View Datasheet(PDF) - Microchip Technology
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MFG CO.
'PIC16CR58A-04I/SO' PDF : 217 Pages View PDF
7.5 Device Reset Timer (DRT)
The Device Reset Timer (DRT) provides a fixed 18 ms
nominal time-out on reset. The DRT operates on an
internal RC oscillator. The processor is kept in RESET
as long as the DRT is active. The DRT delay allows
VDD to rise above VDD min., and for the oscillator to
stabilize.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the device in a RESET condition for approximately 18
ms after the voltage on the MCLR/VPP pin has
reached a logic high (VIH) level. Thus, external RC
networks connected to the MCLR input are not
required in most cases, allowing for savings in
cost-sensitive and/or space restricted applications.
The Device Reset time delay will vary from device to
device due to VDD, temperature, and process
variation. See AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out. This is particularly important for applications
using the WDT to wake the PIC16C5X from SLEEP
mode automatically.
PIC16C5X
7.6 Watchdog Timer (WDT) (not
implemented on PIC16C52)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run even if the clock on the OSC1/CLKIN
and OSC2/CLKOUT pins have been stopped, for
example, by execution of a SLEEP instruction. During
normal operation or SLEEP, a WDT reset or wake-up
reset generates a device RESET.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer reset.
The WDT can be permanently disabled by
programming the configuration bit WDTE as a '0'
(Section 7.1). Refer to the PIC16C5X Programming
Specifications (Literature Number DS30190) to
determine how to access the configuration word.
7.6.1 WDT PERIOD
The WDT has a nominal time-out period of 18 ms,
(with no prescaler). If a longer time-out period is
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT (under software control)
by writing to the OPTION register. Thus, time-out a
period of a nominal 2.3 seconds can be realized.
These periods vary with temperature, VDD and
part-to-part process variations (see DC specs).
Under worst case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
7.6.2 WDT PROGRAMMING CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it
from timing out and generating a device RESET.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum SLEEP time before a WDT wake-up reset.
© 1998 Microchip Technology Inc.
Preliminary
DS30453B-page 39
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