PIC16F1526 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC16F1526' PDF : 354 Pages View PDF
PIC16(L)F1526/27
7.6.9 PIR4 REGISTER
The PIR4 register contains the interrupt flag bits, as
shown in Register 7-9.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 7-9: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4
R/W-0/0
CCP10IF
bit 7
R/W-0/0
CCP9IF
R-0/0
RC2IF
R-0/0
TX2IF
R/W-0/0
CCP8IF
R/W-0/0
CCP7IF
R/W-0/0
BCL2IF
R/W-0/0
SSP2IF
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
CCP10IF: CCP10 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 6
CCP9IF: CCP9 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5
RC2IF: USART2 Receive Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4
TX2IF: USART2 Transmit Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3
CCP8IF: CCP8 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2
CCP7IF: CCP7 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1
BCL2IF: MSSP2 Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0
SSP2IF: Synchronous Serial Port (MSSP2) Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
DS41458B-page 88
Preliminary
2011 Microchip Technology Inc.
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