PIC16LC72A-20E/P View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC16LC72A-20E/P' PDF : 120 Pages View PDF
PIC16C62B/72A
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Description:
Bit Test f, Skip if Set
[label] BTFSS f,b
0 ≤ f ≤ 127
0≤b<7
skip if (f<b>) = 1
None
If bit ’b’ in register ’f’ is ’0’, then the next
instruction is executed.
If bit ’b’ is ’1’, then the next instruction
is discarded and a NOP is executed
instead, making this a 2TCY instruc-
tion.
CLRF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Clear f
[label] CLRF f
0 ≤ f ≤ 127
00h → (f)
1→Z
Z
The contents of register ’f’ are cleared
and the Z bit is set.
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Description:
Bit Test, Skip if Clear
[label] BTFSC f,b
0 ≤ f ≤ 127
0≤b≤7
skip if (f<b>) = 0
None
If bit ’b’ in register ’f’ is ’1’, then the next
instruction is executed.
If bit ’b’ in register ’f’ is ’0’, then the next
instruction is discarded, and a NOP is
executed instead, making this a 2TCY
instruction.
CLRW
Syntax:
Operands:
Operation:
Status Affected:
Description:
Clear W
[ label ] CLRW
None
00h → (W)
1→Z
Z
W register is cleared. Zero bit (Z) is
set.
CALL
Syntax:
Operands:
Operation:
Status Affected:
Description:
Call Subroutine
[ label ] CALL k
0 ≤ k ≤ 2047
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
None
Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
eleven bit immediate address is loaded
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALL is a two cycle instruction.
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Description:
Clear Watchdog Timer
[ label ] CLRWDT
None
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
TO, PD
CLRWDT instruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD
are set.
DS35008B-page 70
Preliminary
© 1999 Microchip Technology Inc.
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