PIC16LC84-04ISO View Datasheet(PDF) - Microchip Technology
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MFG CO.
'PIC16LC84-04ISO' PDF : 110 Pages View PDF
PIC16C84
4.2 Data Memory Organization
The data memory is partitioned into two areas. The first
is the Special Function Registers (SFR) area, while the
second is the General Purpose Registers (GPR) area.
The SFRs control the operation of the device.
Portions of data memory are banked. This is for both
the SFR area and the GPR area. The GPR area is
banked to allow greater than 116 bytes of general
purpose RAM. The banked areas of the SFR are for the
registers that control the peripheral functions. Banking
requires the use of control bits for bank selection.
These control bits are located in the STATUS Register.
Figure 4-2 shows the data memory map organization.
Instructions MOVWF and MOVF can move values from
the W register to any location in the register file (“F”),
and vice-versa.
The entire data memory can be accessed either
directly using the absolute address of each register file
or indirectly through the File Select Register (FSR)
(Section 4.5). Indirect addressing uses the present
value of the RP1:RP0 bits for access into the banked
areas of data memory.
Data memory is partitioned into two banks which
contain the general purpose registers and the special
function registers. Bank 0 is selected by clearing the
RP0 bit (STATUS<5>). Setting the RP0 bit selects
Bank 1. Each Bank extends up to 7Fh (128 bytes). The
first twelve locations of each Bank are reserved for the
Special Function Registers. The remainder are Gen-
eral Purpose Registers implemented as static RAM.
4.2.1 GENERAL PURPOSE REGISTER FILE
All devices have some amount of General Purpose
Register (GPR) area. Each GPR is 8 bits wide and is
accessed either directly or indirectly through the FSR
(Section 4.5).
The GPR addresses in bank 1 are mapped to
addresses in bank 0. As an example, addressing loca-
tion 0Ch or 8Ch will access the same GPR.
4.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (Figure 4-2 and
Table 4-1) are used by the CPU and Peripheral
functions to control the device operation. These
registers are static RAM.
The special function registers can be classified into two
sets, core and peripheral. Those associated with the
core functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for that specific feature.
FIGURE 4-2: REGISTER FILE MAP
File Address
File Address
00h Indirect addr.(1) Indirect addr.(1) 80h
01h
TMR0
OPTION
81h
02h
PCL
PCL
82h
03h
STATUS
STATUS
83h
04h
FSR
FSR
84h
05h
PORTA
TRISA
85h
06h
PORTB
TRISB
86h
07h
87h
08h
EEDATA
EECON1
88h
09h
EEADR
EECON2(1)
89h
0Ah
PCLATH
PCLATH
8Ah
0Bh
INTCON
INTCON
8Bh
0Ch
36
General
Purpose
registers
(SRAM)
8Ch
Mapped
(accesses)
in Bank 0
2Fh
AFh
30h
B0h
7Fh
FFh
Bank 0
Bank 1
Unimplemented data memory location; read as '0'.
Note 1: Not a physical register.
DS30445D-page 12
1996-2013 Microchip Technology Inc.
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