PIC16LC84T-10I/P View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC16LC84T-10I/P' PDF : 110 Pages View PDF
PIC16C84
TABLE 4-1 REGISTER FILE SUMMARY
Address Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note3)
Bank 0
00h
INDF
Uses contents of FSR to address data memory (not a physical register)
---- ---- ---- ----
01h
TMR0
8-bit real-time clock/counter
xxxx xxxx uuuu uuuu
02h
PCL
Low order 8 bits of the Program Counter (PC)
0000 0000 0000 0000
03h
STATUS (2) IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
04h
FSR
Indirect data memory address pointer 0
xxxx xxxx uuuu uuuu
05h
PORTA
—
—
—
RA4/T0CKI
RA3
RA2
RA1
RA0 ---x xxxx ---u uuuu
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1 RB0/INT xxxx xxxx uuuu uuuu
07h
Unimplemented location, read as '0'
---- ---- ---- ----
08h
EEDATA
EEPROM data register
xxxx xxxx uuuu uuuu
09h
EEADR
EEPROM address register
xxxx xxxx uuuu uuuu
0Ah
PCLATH
—
—
—
Write buffer for upper 5 bits of the PC (1)
---0 0000 ---0 0000
0Bh
INTCON
GIE
EEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000u
80h
INDF
Bank 1
Uses contents of FSR to address data memory (not a physical register)
---- ---- ---- ----
81h
OPTION_
REG
RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
82h
PCL
Low order 8 bits of Program Counter (PC)
83h
STATUS (2) IRP
RP1
RP0
TO
PD
Z
DC
84h
FSR
Indirect data memory address pointer 0
85h
TRISA
—
—
— PORTA data direction register
86h
TRISB
PORTB data direction register
87h
Unimplemented location, read as '0'
88h
EECON1
—
—
—
EEIF
WRERR WREN WR
PS0
1111 1111 1111 1111
0000 0000 0000 0000
C
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
---1 1111 ---1 1111
1111 1111 1111 1111
---- ---- ---- ----
RD
---0 x000 ---0 q000
89h
EECON2
EEPROM control register 2 (not a physical register)
---- ---- ---- ----
0Ah
PCLATH
—
—
—
Write buffer for upper 5 bits of the PC (1)
---0 0000 ---0 0000
0Bh
INTCON
GIE
EEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000u
Legend: x = unknown, u = unchanged. - = unimplemented read as '0', q = value depends on condition.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> is never transferred
to PCLATH.
2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset.
3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1996-2013 Microchip Technology Inc.
DS30445D-page 13
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