FIGURE 9-4:
BLOCK DIAGRAM OF
RB4 PIN
WPUBx(2)
Data Bus
WR LATB
or
PORTB
Data Latch
DQ
CK
TRIS Latch
DQ
VDD
P
Weak
Pull-up
I/O
pin(1)
WR TRISB
CK
TTL
Input
Buffer
RD TRISB
RD LATB
Latch
QD
RD PORTB
EN
Q4
WR IOCB
Set RBIF
IOCB Register
DQ
CK
From other
RB pins
CLKOUT
QD
RD PORTB
EN
Q3
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the WPUB bit(s) and RBPU bit.
PIC18F010/020
FIGURE 9-5:
BLOCK DIAGRAM OF
RB5 PIN
WPUBx(2)
Data Bus
WR LATB
or
PORTB
Data Latch
DQ
CK
TRIS Latch
DQ
VDD
P
Weak
Pull-up
I/O
pin(1)
WR TRISB
CK
TTL
Input
Buffer
ST
Buffer
RD TRISB
RD LATB
Latch
QD
RD PORTB
EN
Q4
WR IOCB
IOCB Register
DQ
CK
From other
RB pins
CLKIN
QD
RD PORTB
EN
Q3
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the WPUB bit(s) and RBPU bit.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 69