PIC18F010T-I/P View Datasheet(PDF) - Microchip Technology
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MFG CO.
'PIC18F010T-I/P' PDF : 176 Pages View PDF
PIC18F010/020
6.4.2 TABLAT - TABLE LATCH REGISTER
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold 8-
bit data during data transfers between program mem-
ory and data memory.
6.4.3
TBLPTR - TABLE POINTER
REGISTER
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers (Table Pointer Upper byte, High
byte and Low byte). These three registers
(TBLPTRU:TBLPTRH:TBLPTRL) join to form a 22-bit
wide pointer. The low order 21-bits allow the device to
address up to 2 Mbytes of program memory space. The
22nd bit allows access to the Device ID, the User ID
and the Configuration bits.
The table pointer TBLPTR is used by the TBLRD and
TBLWT instructions. These instructions can update the
TBLPTR in one of four ways, based on the table oper-
ation. These operations are shown in Table 6-1. These
operations on the TBLPTR only affect the low order
21-bits.
TABLE 6-1:
Example
TBLRD*
TBLWT*
TBLRD*+
TBLWT*+
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer
TBLPTR is not modified
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 53
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