PIC18F010/020
REGISTER 12-2: CONFIG1L: CONFIGURATION BYTE (ADDRESS 300000h)
U-0
—
bit 7
R/P-1
TR1
R/P-1
TW1
R/P-1
CP1
R/P-1
DP
R/P-1
TR0
R/P-1
TW0
R/P-1
CP0
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
TR1: Table Read Protection bit (memory area > 0400h byte address)
1 = Table reads are enabled
0 = Table reads are disabled from access outside of this block
bit 5
TW1: Table Write Protection bit (memory area > 0400h byte address)
1 = Table writes are enabled
0 = Table writes are disabled from access outside of this block
bit 4
CP1: Code Protection bit (memory area > 0400h byte address)
1 = Program memory code protection off
0 = Program memory code protected
bit 3
DP: Data Protection bit for EEDATA Memory
1 = External reads and writes are enabled
0 = External reads and writes are disabled
bit 2
TR0: Table Read Protection bit (memory area > 0000h - 03FFh byte address)
1 = Table reads are enabled
0 = Table reads are disabled from access outside of this block
bit 1
TW0: Table Write Protection bit (memory area > 0000h - 03FFh byte address)
1 = Table writes are enabled
0 = Table writes are disabled from access outside of this block
bit 0
CP0: Code Protection bit (memory area > 0000h - 03FFh byte address)
1 = Program memory code protection off
0 = Program memory code protected
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
1 = Bit is set
U = Unimplemented bit, read as ‘0’
0 = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 85