PIC18F010T-I/SN View Datasheet(PDF) - Microchip Technology
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MFG CO.
'PIC18F010T-I/SN' PDF : 176 Pages View PDF
6.3 Erasing FLASH Program Memory
Word erase in the FLASH array is not supported. The
minimum erase block is one row of a panel, which is
equivalent to 16 words or 32 bytes.
Erase operations may be commanded from one of two
sources. Under user program control, the minimum one
row of memory is erased. Under programmer or
ICSPTM control, larger blocks of program memory may
be bulk erased.
6.3.1
ERASING FLASH PROGRAM
MEMORY IN OPERATIONAL MODE
In normal mode, a block of 32 bytes of program mem-
ory is erased. The Most Significant 16 bits of the
TBLPTR<21:6> points to the block being erased.
TBLPTR<4:0> are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the FLASH pro-
gram memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
For protection, the write initiate sequence for EECON2
must be used. When the WR bit is set, a long write is nec-
essary for erasing the internal FLASH. Instruction execu-
tion is halted while in a long write cycle. The long write will
be terminated by the internal programming timer. Instruc-
tion execution will resume with no lost instructions.
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer with address of row being
erased.
2. Set FREE bit to enable row erase; set WREN bit
to enable writes and set EEPGD bit to point to
program memory.
3. Disable interrupts.
4. Write ’55’ to EECON2.
5. Write 'AA’ to EECON2.
6. Set the WR bit. This will begin the row erase cycle.
7. CPU will stall for duration of the erase (about
2ms using internal timer).
PIC18F010/020
6.4 FLASH Array Programming
Operations
Word or byte programming is not supported. The mini-
mum programming block is 32-bits or 2 words.
6.4.1
PROGRAMMING FLASH PROGRAM
MEMORY IN OPERATIONAL MODE
(TABLE LONG WRITES)
Conceptually, Table Writes are performed one byte at a
time. The instruction will write one byte contained in the
TABLAT register to the internal memory, pointed to by
the TBLPTR, as shown in Figure 6-3.
The TBLPTR can be updated in one of four ways,
based on the Table Write instructions:
• TBLWT* no-change
• TBLWT*+ post-increment
• TBLWT*- post-decrement
• TBLWT+* pre-increment
The program memory FLASH uses a similar mecha-
nism to the data EEPROM. Table Writes are used inter-
nally to load the Write registers used to program the
FLASH memory. The EECON1 register is used to actu-
ally command a write or erase event.
Each FLASH panel is programmed with 32 of 256 columns
at a time. This translates into 32 write bit latches. These
write latches are accessed using Table Write instructions,
which can write a byte at a time. There are then 4 Table
Writes required to write the latches for one panel.
Since the table latch is only a single byte, the TBLWT
instruction has to be executed 4 times for each pro-
gramming operation. All of the Table Write operations
will essentially be short writes, because only the table
latches are written. At the end of updating 4 latches, the
EECON1 register must be written to start the program-
ming operation with a long write.
The long write is necessary for programming the inter-
nal FLASH. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer. Instruction execution
will resume with two lost instructions.
The write time is controlled by the EEPROM on-chip
timer. The write/erase voltages are generated by an on-
chip charge pump, rated to operate over the voltage
range of the device for byte or word operations. When
doing block operations, the device must be operating in
the 5V ±10% range.
Note:
When writing a block, insure the table
pointer is pointing to the desired block after
the last short write.
The first and second instruction following
the TBLWT must be NOPs.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 49
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