PIC18F010T View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18F010T' PDF : 176 Pages View PDF
PIC18F010/020
TABLE 13-2: PIC18F010/020 INSTRUCTION SET
Mnemonic,
Operands
Description
16-Bit Instruction Word
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
SUBWF
SUBWFB
SWAPF
TSTFSZ
XORWF
f [,d] [,a]
f [,d] [,a]
f [,d] [,a]
f [,a]
f [,d] [,a]
f [,a]
f [,a]
f [,a]
f [,d] [,a]
f [,d] [,a]
f [,d] [,a]
f [,d] [,a]
f [,d] [,a]
f [,d] [,a]
f [,d] [,a]
f [,d] [,a]
fs, fd
f [,a]
f [,a]
f [,a]
f [,d] [,a]
f [,d] [,a]
f [,d] [,a]
f [,d] [,a]
f [,a]
f [,d] [,a]
f [,d] [,a]
f [,d] [,a]
f [,d] [,a]
f [,a]
f [,d] [,a]
Add WREG and f
Add WREG and Carry bit to f
AND WREG with f
Clear f
Complement f
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move f
Move fs (source) to 1st word
fd (destination)2nd word
Move WREG to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
borrow
Subtract WREG from f
Subtract WREG from f with
borrow
Swap nibbles in f
Test f, skip if 0
Exclusive OR WREG with f
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2
1
1
1
1
1
1
1
1
1
0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
1
0101 11da
1
0101 10da
1
0011 10da
1 (2 or 3) 0110 011a
1
0001 10da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
None
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N
1, 2, 6
1, 2, 6
1,2, 6
2, 6
1, 2, 6
4, 6
4, 6
1, 2, 6
1, 2, 3, 4, 6
1, 2, 3, 4, 6
1, 2, 6
1, 2, 3, 4, 6
4, 6
1, 2, 6
1, 2, 6
1, 6
6
6
1, 2, 6
6
1, 2, 6
6
6
6
1, 2, 6
ffff C, DC, Z, OV, N 6
ffff C, DC, Z, OV, N 1, 2, 6
ffff None
ffff None
ffff Z, N
4, 6
1, 2, 6
6
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b [,a]
f, b [,a]
f, b [,a]
f, b [,a]
f [,d] [,a]
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
1
1001
1
1000
1 (2 or 3) 1011
1 (2 or 3) 1010
1
0111
bbba
bbba
bbba
bbba
bbba
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
None
None
None
None
None
1, 2, 6
1, 2, 6
3, 4, 6
3, 4, 6
1, 2, 6
Note 1:
2:
3:
4:
5:
6:
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ’0’.
If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP, unless the
first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.
If the table write starts the write cycle to internal memory, the write will continue until terminated.
Microchip Assembler MASM automatically defaults destination bit ’d’ to ’1’, while access bit ’a’ defaults to ’1’ or ’0’
according to address of register being used.
DS41142A-page 98
Preliminary
2001 Microchip Technology Inc.
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