PIC18F24J10 View Datasheet(PDF) - Microchip Technology
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MFG CO.
'PIC18F24J10' PDF : 368 Pages View PDF
PIC18F45J10 FAMILY
6.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
6.5.4
PROTECTION AGAINST
SPURIOUS WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 20.0 “Special Features of the
CPU” for more detail.
6.6 Flash Program Operation During
Code Protection
See Section 20.6 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Name
Bit 7
Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
page
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 43
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
43
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
43
TABLAT Program Memory Table Latch
43
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF
RBIF
43
EECON2 EEPROM Control Register 2 (not a physical register)
45
EECON1
—
—
—
FREE WRERR WREN
WR
—
45
IPR2
OSCFIP CMIP
—
—
BCL1IP
—
—
CCP2IP
45
PIR2
OSCFIF CMIF
—
—
BCL1IF
—
—
CCP2IF
45
PIE2
OSCFIE CMIE
—
—
BCL1IE
—
—
CCP2IE
45
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 75
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