PIC18F24J10 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18F24J10' PDF : 368 Pages View PDF
PIC18F45J10 FAMILY
REGISTER 8-11:
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
R/W1
U-0
U-0
R/W-1
U-0
OSCFIP CMIP
—
—
BCL1IP
—
bit 7
U-0
R/W-1
—
CCP2IP
bit 0
bit 7
bit 6
bit 5-4
bit 3
bit 2-1
bit 0
OSCFIP: Oscillator Fail Interrupt Priority bit
1 = High priority
0 = Low priority
CMIP: Comparator Interrupt Priority bit
1 = High priority
0 = Low priority
Unimplemented: Read as ‘0’
BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module)
1 = High priority
0 = Low priority
Unimplemented: Read as ‘0’
CCP2IP: CCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
REGISTER 8-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1 R/W-1
U-0
U-0
U-0
U-0
U-0
U-0
SSP2IP BCL2IP
—
—
—
—
—
—
bit 7
bit 0
bit 7
bit 6
bit 5-0
SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit
1 = High priority
0 = Low priority
BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module)
1 = High priority
0 = Low priority
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 89
Share Link: 
