PIC18F6310 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18F6310' PDF : 404 Pages View PDF
PIC18F6310/6410/8310/8410
7.0 EXTERNAL MEMORY
INTERFACE
Note:
The external memory interface is not
implemented on PIC18F6310 and
PIC18F6410 (64-pin) devices.
The external memory interface allows the device to
access external memory devices (such as Flash,
EPROM, SRAM, etc.) as program or data memory. It is
implemented with 28 pins, multiplexed across four I/O
ports. Three ports (PORTD, PORTE and PORTH) are
multiplexed with the address/data bus for a total of 20
available lines, while PORTJ is multiplexed with the
bus control signals. A list of the pins and their functions
is provided in Table 7-1.
As implemented here, the interface is similar to that
introduced on PIC18F8X20 microcontrollers. The most
notable difference is that the interface on
PIC18F8310/8410 devices supports both 16-bit and
Multiplexed 8-bit Data Width modes; it does not support
the 8-bit Demultiplexed mode. The bus width mode is
set by the BW configuration bit when the device is
programmed and cannot be changed in software.
The operation of the interface is controlled by the
MEMCON register (Register 7-1). Clearing the EBDIS
bit (MEMCON<7>) enables the interface and disables
the I/O functions of the ports, as well as any other mul-
tiplexed functions. Setting the bit disables the interface
and enables the ports.
For a more complete discussion of the operating
modes that use the external memory interface, refer to
Section 7.1 “Program Memory Modes and the
External Memory Interface”.
REGISTER 7-1:
MEMCON: MEMORY CONTROL REGISTER
R/W-0
U-0
R/W-0 R/W-0
U-0
EBDIS
—
WAIT1 WAIT0
—
bit7
U-0
R/W-0 R/W-0
—
WM1
WM0
bit0
bit 7
bit 6
bit 5-4
bit 3-2
bit 1-0
EBDIS: External Bus Disable bit
1 = External system bus disabled, all external bus drivers are mapped as I/O ports
0 = External system bus enabled, I/O ports are disabled
Unimplemented: Read as ‘0’
WAIT1:WAIT0: Table Reads and Writes Bus Cycle Wait Count bits
11 = Table reads and writes will wait 0 TCY
10 = Table reads and writes will wait 1 TCY
01 = Table reads and writes will wait 2 TCY
00 = Table reads and writes will wait 3 TCY
Unimplemented: Read as ‘0’
WM1:WM0: TBLWRT Operation with 16-bit Bus Width bits
1x = Word Write mode: TABLAT0 and TABLAT1 word output, WRH active when TABLAT1
is written
01 = Byte Select mode: TABLAT data copied on both MSB and LSB, WRH and (UB or LB)
will activate
00 = Byte Write mode: TABLAT data copied on both MSB and LSB, WRH or WRL will activate
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc.
Preliminary
DS39635A-page 89
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