PIC18LF010T-I View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18LF010T-I' PDF : 176 Pages View PDF
PIC18F010/020
REGISTER 5-1:
EECON1 REGISTER (ADDRESS 18Ch)
R/W-U
U-0
EEPGD
—
bit 7
U-0
R/W-0
—
FREE
R/W-x
WRERR
R/W-0
WREN
R/S-0
WR
R/S-0
RD
bit 0
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
EEPGD: FLASH Program or Data EEPROM Memory Select bit
1 = Access Program FLASH memory
0 = Access Data EEPROM memory
Unimplemented: Read as ‘0’
FREE: FLASH Row Erase Enable bit
1 = Erase the row addressed by TBLPTR on the next WR command (reset by hardware)
0 = Perform write only
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR Reset or any WDT Reset during normal operation)
0 = The write operation completed
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
WR: Write Control bit
1 = Initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR
bit can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD
bit can only be set (not cleared) in software.)
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS41142A-page 44
Preliminary
2001 Microchip Technology Inc.
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