PIC24HJ128GP202 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC24HJ128GP202' PDF : 357 Pages View PDF
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
8.1 DMAC Registers
Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)
contains the following registers:
• A 16-bit DMA Channel Control register
(DMAxCON)
• A 16-bit DMA Channel IRQ Select register
(DMAxREQ)
• A 16-bit DMA RAM Primary Start Address register
(DMAxSTA)
• A 16-bit DMA RAM Secondary Start Address
register (DMAxSTB)
• A 16-bit DMA Peripheral Address register
(DMAxPAD)
• A 10-bit DMA Transfer Count register (DMAxCNT)
An additional pair of status registers, DMACS0 and
DMACS1, are common to all DMAC channels.
DMACS0 contains the DMA RAM and SFR write
collision flags, XWCOLx and PWCOLx, respectively.
DMACS1 indicates DMA channel and Ping-Pong mode
status.
The DMAxCON, DMAxREQ, DMAxPAD and
DMAxCNT are all conventional read/write registers.
Reads of DMAxSTA or DMAxSTB reads the contents
of the DMA RAM Address register. Writes to
DMAxSTA or DMAxSTB write to the registers. This
allows the user to determine the DMA buffer pointer
value (address) at any time.
The interrupt flags (DMAxIF) are located in an IFSx
register in the interrupt controller. The corresponding
interrupt enable control bits (DMAxIE) are located in
an IECx register in the interrupt controller, and the
corresponding interrupt priority control bits (DMAxIP)
are located in an IPCx register in the interrupt
controller.
© 2009 Microchip Technology Inc.
Preliminary
DS70293D-page 109
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