PIC24HJ128GP202 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC24HJ128GP202' PDF : 357 Pages View PDF
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
REGISTER 3-2: CORCON: CORE CONTROL REGISTER
U-0
—
bit 15
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
—
—
bit 8
U-0
—
bit 7
U-0
U-0
U-0
R/C-0
R/W-0
U-0
U-0
—
—
—
IPL3(1)
PSV
—
—
bit 0
Legend:
R = Readable bit
0’ = Bit is cleared
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 15-4
bit 3
bit 2
bit 1-0
Unimplemented: Read as ‘0’
IPL3: CPU Interrupt Priority Level Status bit 3(1)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
Unimplemented: Read as ‘0’
Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
© 2009 Microchip Technology Inc.
Preliminary
DS70293D-page 23
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