PKS606P View Datasheet(PDF) - Power Integrations, Inc
Part Name
Description
MFG CO.
PKS606P
PeakSwitch Family Enhanced, Energy-Efficient, Off-Line Switcher IC With Super Peak Power Performance
Power Integrations, Inc
'PKS606P' PDF : 24 Pages View PDF
PKS603-607
BYPASS
(BP)
240 A
25 A
ENABLE
LINE UNDER-VOLTAGE
FAULT
LATCH OFF/ PRESENT
AUTO-
RESTART
COUNTER
ON TIME EXT
6.3 V
RESET
REGULATOR
5.8 V
CURRENT
LIMIT STATE
MACHINE/
ADAPTIVE
CURRENT
LIMIT
+
-
5.8 V
4.8 V
BYPASS PIN
UNDER-VOLTAGE
VILIMIT
CURRENT LIMIT
COMPARATOR
DRAIN
(D)
1.0 V + VT
ENABLE/
UNDER-
VOLTAGE
(EN/UV)
1.0 V
JITTER
CLOCK
DCMAX
OSCILLATOR
Figure 2. Functional Block Diagram.
Pin Functional Description
DRAIN (D) Pin:
The power MOSFET drain connection provides internal
operating current for both startup and steady-state operation.
BYPASS (BP) Pin:
A 0.33 µF external bypass capacitor for the internally generated
5.8 V supply is connected to this pin. In typical applications,
this pin must be externally supplied via a bias winding.
ENABLE/UNDER-VOLTAGE (EN/UV) Pin:
This pin has dual functions: enable input and line under-voltage
sense. During normal operation, switching of the power MOSFET
is controlled by this pin. MOSFET switching is disabled when a
current greater than 240 µA is drawn from this pin. This pin may
also sense line under-voltage conditions through either an external
resistor connected to the DC line voltage or an AC sense circuit.
SOURCE (S) Pin:
This is the MOSFET source connection for high voltage return
and control circuit common.
THERMAL
SHUTDOWN
S
Q
R
Q
LEADING
EDGE
BLANKING
SOURCE
(S)
GROUND (GND)
(Y & F Package
Only)
PI-3940-040606
Y Package (TO-220-7C)
Tab Internally
Connected to
SOURCE Pin
7D
5 NC
4S
3 EN/UV
2 GND
1 BP
P Package (DIP-8C) F Package (TO-262-7C)
BP 1
EN/UV 2
D4
8S
7S
6S
5S
Figure 3. Pin Configuration.
7D
5 NC
4S
3 EN/UV
2 GND
1 BP
PI-3941-031506
GROUND (GND) Pin (Y or F Package Only):
This is the signal ground for the bypass capacitor and optocoupler.
2
Rev. I 02/07
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