PM3350 View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM3350' PDF : 224 Pages View PDF
ELAN 8X10
DATA SHEET
PMC-970109
ISSUE 3
PM3350 ELAN 8 X10
8 PORT ETHERNET SWITCH
PCI Expansion Bus Interface
Signal Name Size
AD[31:0]
32
CBE_[3:0]
4
PAR
1
FRAME_
1
IRDY_
1
TRDY_
1
STOP_
1
DEVSEL_
1
IDSEL
1
REQ_
1
GNT_
1
INT_
1
PERR_
1
SERR_
1
PCI_CLK
1
Type Description
I/O Multiplexed PCI address/data bus, used by an external bus master (e.g., a PCI
host) or the ELAN 8x10 to transfer addresses or data.
I/O Command/Byte-Enable lines. These lines supply a command (during PCI address
phases) or byte enables (during data phases) for each bus transaction.
I/O Address/data/command parity, supplies the even parity computed over the
AD[31:0] and CBE_[3:0] lines during valid data phases; it is sampled (when the
ELAN 8x10 is acting as a target) or driven (when the ELAN 8x10 acts as an
initiator) one clock edge after the respective data phase.
I/O Bus transaction delimiter (framing signal); a HIGH-to-LOW transition on this signal
indicates that a new transaction is beginning (with an address phase); a LOW-to-
HIGH transition indicates that the next valid data phase will end the currently
ongoing transaction.
I/O Transaction Initiator (master) ready, used by the transaction initiator or bus master
to indicate that it is ready for a data transfer. A valid data phase ends with data
transfer when both IRDY_ and TRDY_ are sampled asserted on the same clock
edge.
I/O Transaction Target ready, used by the transaction target or bus slave to indicate
that it is ready for a data transfer. A valid data phase ends with data transfer when
both IRDY_ and TRDY_ are sampled asserted on the same clock edge.
I/O Transaction termination request, driven by the current target or slave to abort,
disconnect or retry the current transfer.
I/O Device select acknowledge: driven by a target to indicate to the initiator that the
address placed on the AD[31:0] lines (together with the command on the
CBE_[3:0] lines) has been decoded and accepted as a valid reference to the
target's address space. Once asserted, it is held asserted until FRAME_ is
de-asserted; otherwise, it indicates (in conjunction with STOP_ and TRDY_) a
target-abort.
I Device identification (slot) select. Assertion of IDSEL signals the ELAN 8x10 that it
is being selected for a configuration space access.
O Bus request (to bus arbiter), asserted by the ELAN 8x10 to request control of the
PCI bus.
I Bus grant (from bus arbiter); this indicates to the ELAN 8x10 that it has been
granted control of the PCI bus, and may begin driving the address/data and control
lines after the current transaction has ended (indicated by FRAME_, IRDY_ and
TRDY_ all de-asserted simultaneously).
OD Open Drain Interrupt request. This pin signals an interrupt request to an external
PCI host system. The INT_ pin should be tied to the INTA* line on the PCI bus.
I/O Bus parity error signal, asserted by the ELAN 8x10 as a bus slave, or sampled by
the ELAN 8x10 as a bus master, to indicate a parity error on the AD[31:0] and
CBE_[3:0] lines.
OD Open Drain System error, used by the ELAN 8x10 to indicate a system error, or a
parity error on the AD[31:0] and CBE_[3:0] lines during an address phase.
I PCI bus clock; supplies the PCI bus clock signal to the ELAN 8x10.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY
22
Share Link: 
