PM4328 View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM4328' PDF : 250 Pages View PDF
STANDARD PRODUCT
DATASHEET
PMC-2011596
ISSUE 1
Figure 17: Clock Slave: External Signaling
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
ED[1:28]
ES IG [1 :2 8 ]
CEFP
CECLK
Inputs Tim ed
to CECLK
ESIF
Egress
System
Inte rface
T 1 -X B AS/E 1 -T R AN
BasicTransm itter:
Frame Generation,
Alarm Insertion,
Signaling Insertion,
Trunk Conditioning
Line Coding
T R AN S M IT TE R
T J AT
Digital PLL
T J AT
FIFO
Transmit C LK[1:28]
Transmit D ata[1:28]
In Clock Slave: External Signaling mode, the egress interface is clocked by the
common egress clock, CECLK. The transmitter is either frame-aligned or
superframe-aligned to the common egress frame pulse, CEFP, via the CEMFP
bit in the Master Egress Slave Mode Serial Interface Configuration register. The
ESIG[x] signal contains the robbed-bit signaling data to be inserted into Transmit
Data[x], with the four least significant bits of each channel on ESIG[x]
representing the signaling state (ABCD or ABAB in T1 SF mode). EFP[x] is not
available in this mode.
Figure 18: Clock Slave: Clear Channel
T R AN S M IT TE R
E D [1 :2 8 ]
ECLK[1:28]
Input Tim ed
to ECLK[x]
ESIF
Egress
System
Inte rface
T J AT
Digital PLL
T J AT
FIFO
Transmit C LK[1:28]
Transmit D ata[1:28]
In Clock Slave: Clear Channel mode, the egress interface is clocked by the
externally provided egress clock, ECLK[x]. ECLK[x] must be a 1.544 MHz clock
for T1 links or a 2.048 MHz clock for E1 links. In this mode the T1/E1 framers are
bypassed except for the TJAT which may or may not be bypassed depending on
the setting of the TJATBYP bit in the T1/E1 Egress Line Interface Options
register. Typically the TJAT would be bypassed unless jitter attenuation is
required on ECLK[x].
PROPRIETARY AND CONFIDENTIAL
88
Share Link: 
