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PM4328 View Datasheet(PDF) - PMC-Sierra

Part Name
Description
MFG CO.
'PM4328' PDF : 250 Pages View PDF
STANDARD PRODUCT
DATASHEET
PMC-2011596
ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
The bit error rate for T1 ESF can be calculated from the one-second PMON
CRCE count by the following equation:
çæ
ç
log çèæ 1- 802040
BEE
÷ö
ø
÷ö
÷
ç
Bit Error Rate = 1 - 10 ççè
24*193
÷
÷÷ø
Figure 31: CRCE Count vs. BER (T1 ESF mode)
1.00E-02
1.00E-03
1.00E-04
1.00E-05
1.00E-06
1.00E-07
0
50 100 150 200 250 300 350
CRCE
For T1 SF format, the CRCE and FER counts are identical, but the FER counter
is smaller and should be ignored.
Figure 32: CRCE Count vs. BER (T1 SF mode)
20
18
)
2-10
16
14
x(
ae t
12
10
REorrr t i
B
8
6
4
2
0
0
Average Count Over
Many 1 Second Intervals
200
400
600
800
1000
Bit Error Event Count Per Second
1200
12.4 Using the Internal FDL Transmitter
It is important to note that access rate to the TDPR registers is limited by the rate
of the internal high-speed system clock which is either the DS3, DS1 or E1 clock.
Consecutive accesses to the TDPR Configuration, TDPR Interrupt Status/UDR
PROPRIETARY AND CONFIDENTIAL
140
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