Qdatasheet_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

PM4328 View Datasheet(PDF) - PMC-Sierra

Part Name
Description
MFG CO.
'PM4328' PDF : 250 Pages View PDF
STANDARD PRODUCT
DATASHEET
PMC-2011596
ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
B24, C1-C24, D1-D24. When using 2 state CAS there are only A1-A24 signaling
bits.
Table 18: T1 Channel Associated Signaling bits
SF ESF
S1
S2
S3
S4
F
F
P1 P0
A1
A2
A3
A4
F1 M1
00
A5
A6
A7
A8
S1 C1
00
A9
A10
A11
A12
F2 M2
00
A13
A14
A15
A16
S2 F1
00
A17
A18
A19
A20
F3 M3
00
A21
A22
A23
A24
S3 C2
00
B1
B2
B3
B4
F4 M4
01
B5
B6
B7
B8
S4 F2
01
B9
B10
B11
B12
F5 M5
01
B13
B14
B15
B16
S5 C3
01
B17
B18
B19
B20
F6 M6
01
B21
B22
B23
B24
S6 F3
01
C1
C2
C3
C4
F1 M7
10
C5
C6
C7
C8
S1 C4
10
C9
C10
C11
C12
F2 M8
10
C13
C14
C15
C16
S2 F4
10
C17
C18
C19
C20
F3 M9
10
C21
C22
C23
C24
S3 C5
10
D1
D2
D3
D4
F4 M10
11
D5
D6
D7
D8
S4 F5
11
D9
D10
D11
D12
F5 M11
11
D13
D14
D15
D16
S5 C6
11
D17
D18
D19
D20
F6 M12
11
D21
D22
D23
D24
S6 F6
11
Note that in synchronous mode, the SF/ESF F-bits may have arbitrary alignment
with respect to the P1P0 phase alignment bits, due to possible frame slips at the
T1 level. However, CAS is always aligned to the P1P0 bits (i.e. in either
synchronous or asynchronous mode).
T1 tributary asynchronous timing is compensated via the V3 octet. T1 tributary
link rate adjustments are optionally passed across the SBI via the V4. T1
tributary alarm conditions are optionally passed across the SBI bus via the link
rate octet in the V4 location.
In synchronous mode the T1 tributary mapping is fixed to that shown in Table 17
and rate justifications are not possible using the V3 octet. The clock rate
PROPRIETARY AND CONFIDENTIAL
164
Share Link: GO URL

All Rights Reserved © qdatasheet.com  [ Privacy Policy ] [ Contact Us ]