PM4328 View Datasheet(PDF) - PMC-Sierra

Part Name

Description

MFG CO.

PM4328

HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER

PMC-Sierra

'PM4328' PDF : 250 Pages View PDF

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STANDARD PRODUCT
DATASHEET
PMC-2011596
ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
5.2 M13 Multiplexer Mode Block Diagram
Figure 4 shows the TECT3, configured as a M13 multiplexer, connected to a
synchronous H-MVIP system side bus. In this example the TECT3 provides
synchronous access to the fully channelized T1s (access to all DS0s)
multiplexed into the DS3. There is also synchronous H-MVIP access to all
channel associated signaling channels (CAS). An additional H-MVIP interface
can be used to provide synchronous access to the common channel signaling
channels (CCS), although this same information is available within the data H-
MVIP signals.
Figure 4: M13 Multiplexer Block Diagram
TOPS
Timing Options
T J AT
Digital Jitter
A tte nuator
T 1 -X B AS/E 1 -T R AN
BasicTransm itte r:
Frame Generation,
Alarm Insertio n,
Sign aling Ins ertio n,
Trunk Conditioning
TPSC
Per-D S0
C o n tro lle r
E SIF
Egress
System
Inte rface
XCLK
CTCLK
CM V 8MC LK
CMVFPB
MVED[1:7]
CASED[1:7]
CCSED
TICLK
TCLK
TPOS/TDAT
TNEG/TMFP
RCLK
RPOS/RDAT
R N EG /R LC V
XBOC
Tx
FEAC
TDPR
Tx
HDLC
B3ZS
Encode
T R AN
DS3
Tra n s m it
Framer
B3ZS
Decode
FRM R
DS3
R ece ive
Framer
RBOC
Rx
FEAC
R D LC
Rx
HDLC
PMON
Perf.
M o n it o r
#1
M X23
M23
MUX/
DEMUX
FRMR MX12
DS2 M12
Framer MUX/
DEMUX
One of Seven
FRMR/M12s
XBOC
Bit O riented
Code
G enerator
TDPR
HDLC
Transmitter
PMON
Performance
M o n ito r
C o u n te rs
RDLC
HDLC
Receiver
T1-APRM
Auto
Performance
Response
Monitor
RBOC
Bit Oriented
Code
Detector
ALM I
A la rm
Inte gra tor
PRBS
Pattern
G e n e r-
a to r/
Detector
R J AT
Digital Jitter
A tte nua to r
One of 28 T1 or
21 E1 Framers
T1 /E1-FRM R
Fram e
Alignm ent,
A la rm
E x tr a c tio n
FRAM
Framer RAM
ELST
Elastic
Store
S IG X
S ig n a lin g
E xtracto r
RPSC
Per-DS0
C o n tr o lle r
ISIF
Ingress
System
Inte rface
MVID[1:7]
CASID[1:7]
CCSID
CIFP
C IC LK/C MVF PC
RECVCLK1
RECVCLK2
5.3 DS3 Framer Only Block Diagram
Figure 5 shows the TECT3 configured as a DS3 framer. In this mode the TECT3
provides access to the full DS3 unchannelized payload. The payload access
(right side of diagram) has two clock and data interfacing modes, one utilizing a
gapped clock to mask out the DS3 overhead bits and the second utilizing an
ungapped clock with overhead indications on a separate overhead signal. The
SBI bus can also be used to provide access to the unchannelized DS3.
PROPRIETARY AND CONFIDENTIAL
18

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