STANDARD PRODUCT
DATASHEET
PMC-2011596
ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Pin Name
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
A[11]
A[12]
A[13]
RSTB
ALE
JTAG Interface
TCK
Type Pin Function
No.
I/O
Input
Input
Input
C14 Bidirectional Data Bus (D[7:0]). This bus provides
B14 TECT3 register read and write accesses.
A14
D14
C13
B13
A13
D13
A17 Address Bus (A[13:0]). This bus selects specific
C16 registers during TECT3 register accesses.
D18
D19
B17
A18
Signal A[13] selects between normal mode and test
mode register access. A[13] has an integral pull down
resistor.
A19
A20
C18
B19
B20
A21
C19
B21
A22 Active Low Reset (RSTB). This signal provides an
asynchronous TECT3 reset. RSTB is a Schmitt
triggered input with an integral pull up resistor.
D17 Address Latch Enable (ALE). This signal is active
high and latches the address bus A[13:0] when low.
When ALE is high, the internal address latches are
transparent. It allows the TECT3 to interface to a
multiplexed address/data bus. The ALE input has an
integral pull up resistor.
Input C3 Test Clock (TCK). This signal provides timing for test
operations that can be carried out using the IEEE
P1149.1 test access port.
PROPRIETARY AND CONFIDENTIAL
48