S TANDARD PRODUCT
PMC-Sierra, Inc.
PM5945 -UTP5
PMC-940202 ISSUE 2. APRIL 7, 1995
APP_SAPI_UTP5
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Microprocessor Interface Write Access
Table 13: Microprocessor Interface Write Access Parameters
Symbol
Parameter
tSDW
Data to Valid Write Set-up Time
tSAW
Address to Valid Write Set-up Time
tHAW
tSDW
Address to Valid Write Hold Time
Data to Valid Write Set-up Time
tHDW
Data to Valid Write Hold Time
tVWR
Valid Write Pulse Width
Min Max Units
20
ns
25
ns
20
ns
20
ns
20
ns
40
ns
Fig . 6 Microprocessor Interface Write Timing
A[8:0]
Valid Address
(CSB+WRB)
D[7:0]
tSAW
tVWR
tH AW
tS DW
tH DW
Valid Data
Notes on Microprocessor Interface Write Timing:
1 A valid write cycle is defined as a logical OR of the CSB and the WRB signals.
2. Microprocessor Interface timing applies to normal mode register accesses only.
3. When a set-up time is specified between an input and a clock, the set-up time is
the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of
the clock.
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