PM6670S View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'PM6670S' PDF : 54 Pages View PDF
PM6670S
Device description
The design of the external feedback network depends on the output voltage ripple. If the
ripple is higher than approximately 20 mV, the correct CINT capacitor is usually enough to
keep the loop stable. The stability of the system depends firstly on the output capacitor zero
frequency.
The following condition must be satisfied:
Equation 6
fSW
>
k ⋅ fZout
=
k
2π ⋅ Cout
⋅ ESR
where k is a fixed design parameter (k > 3). It determines the minimum integrator capacitor
value:
Equation 7
CINT
>
gm
2π ⋅ ⎜⎛ fSW
⎝k
−
fZout
⎟⎞
⎠
⋅
Vr
Vout
where gm = 50 μs is the integrator trans conductance.
In order to ensure stability it must be also verified that:
Equation 8
CINT
>
gm
2π ⋅ fZout
⋅
Vr
VOUT
If the ripple on the COMP pin is greater than the integrator 150 mV, the auxiliary capacitor
CFILT can be added. If q is the desired attenuation factor of the output ripple, CFILT is given
by:
Equation 9
CFILT
=
CINT
⋅ (1− q)
q
In order to reduce the noise on the COMP pin, it is possible to add a resistor RINT that,
together with CINT and CFILT, becomes a low pass filter. The cutoff frequency fCUT must be
much greater (10 or more times) than the switching frequency:
Equation 10
RINT
=
2π ⋅ fCUT
1
⋅ CINT ⋅ CFILT
CINT + CFILT
If the ripple is very small (lower than approximately 20 mV), a different compensation
network, called “Virtual-ESR” network, is needed. This additional circuit generates a
triangular ripple that is added to the output voltage ripple at the input of the integrator. The
complete control scheme is shown in Figure 32.
Doc ID 14432 Rev 4
25/54
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