Device description
PM6685
Figure 30. Circuitry for output ripple compensation
COMP PIN
VOLTAGE
∆V
Vr
t
OUTPUT VOLTAGE
∆V
t
L
COMP
CFILT
CINT
RINT
VCINT
OUT
I=gm(V1-Vr)
Vr
+
gm
+
Vr V1
RFb1
- PWM
Comparator
RFb2
ROUT
D
COUT
The integrator amplifier generates a current, proportional to the DC errors, which decreases
the output voltage in order to compensate the total static error, including the voltage drop on
PCB traces. In addition, CINT provides an AC path for the output ripple. In steady state, the
voltage on COMP5/COMP3 pin is the sum of the reference voltage Vr and the output ripple
(see Figure 30). In fact when the voltage on the COMP pin reaches Vr, a fixed Ton begins
and the output increases.
For example, we consider VOUT=5V with an output ripple of ∆V=50mV. Considering
CINT>>CFILT, the CINT DC voltage drop VCINT is about 5V-Vr+25mV=4.125V. CINT ensures
an AC path for the output voltage ripple. Then the COMP pin ripple is a replica of the output
ripple, with a DC value of Vr+25mV=925mV.
For more details about the output ripple compensation network, see the paragraph “Closing
the integrator loop” in the Design guidelines.
7.4
Pulse skip mode
If the SKIP pin is tied to ground, the device works in skip mode.
At light loads a zero-crossing comparator truncates the low-side switch on-time when the
inductor current becomes negative. In this condition the section works in discontinuous
conduction mode. The threshold between continuous and discontinuous conduction mode
is:
Equation 4
ILOAD(SKIP)
=
VIN − VOUT
2×L
× TON
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