PM7382 View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM7382' PDF : 330 Pages View PDF
RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
Pin Name Type Pin
No.
TMV8DC Input U20
TBD
Input Y5
TBCLK
Tristate AA4
Output
Function
The transmit 8.192 Mbps H-MVIP data clock
signal (TMV8DC) provides the transmit data
clock for links configured to operate in 8.192
Mbps H-MVIP mode.
TMV8DC is used to update data on TD[4m]
(0£m£7) when link 4m is configured for 8.192
Mbps H-MVIP operation. TMV8DC is nominally
a 50% duty cycle clock with a frequency of
16.384 MHz.
TMV8DC is ignored and should be tied low
when no physical links are configured for
operation in 8.192 Mbps H-MVIP mode.
The transmit BERT data signal (TBD) contains
the transmit bit error rate test data. When the
TBERTEN bit in the BERT Control register is set
high, the data on TBD is transmitted on the
selected one of the transmit data signals
(TD[31:0]). TBD is sampled on the rising edge
of TBCLK. BERT is not supported for H-MVIP
links.
The transmit BERT clock signal (TBCLK)
contains the transmit bit error rate test clock.
TBCLK is a buffered version of the selected one
of the transmit clock signals (TCLK[31:0]).
TBCLK may be tristated by setting the TBEN bit
in the FREEDM-32P256 Master BERT Control
register low. BERT is not supported for H-MVIP
links.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 20
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