PPC5553AVR112 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'PPC5553AVR112' PDF : 60 Pages View PDF
Electrical Characteristics
Table 14. Flash Program and Erase Specifications1 (continued)
Num
Characteristic
Symbol
Min
Typ
Initial
Max2
Max3 Unit
10 64 Kbyte Block Pre-program and Erase Time
T64kpperase
—
400
500 5000 ms
8 128 Kbyte Block Pre-program and Erase Time
T128kpperase
—
500 1250 15,000 ms
11 Minimum operating frequency for program and erase
—
25
—
—
— MHz
operations6
1 Typical program and erase times assume nominal supply values and operation at 25 oC.
2 Initial factory condition: ≤ 100 program/erase cycles, 25 oC, typical supply voltage, 80MHz minimum system frequency.
3 The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized
but not guaranteed.
4 Actual hardware programming times. This does not include software overhead.
5 Page size is 256 bits (8 words).
6 Read frequency of the flash can be up to the maximum operating frequency of the device. There is no minimum read frequency
condition.
Table 15. Flash EEPROM Module Life (Full Temperature Range)
Num
Characteristic
Symbol
Min Typical1 Unit
1a Number of Program/Erase cycles per block for 16 Kbyte, 48 Kbyte, and 64
P/E
Kbyte blocks over the operating temperature range (TJ)
100,000 — cycles
1b Number of Program/Erase cycles per block for 128 Kbyte blocks over the
P/E
operating temperature range (TJ)
10,000 100,000 cycles
2 Data retention
Blocks with 0 – 1,000 P/E cycles
Blocks with 1,001 – 100,000 P/E cycles
Retention
20
5
— years
1 Typical endurance is evaluated at 25C. Product qualification is performed to the minimum specification. For additional
information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619 “Typical Endurance
for Nonvolatile Memory.”
Table 16 shows the FLASH_BIU settings versus frequency of operation. Refer to the device Reference
Manual for definitions of these bit-fields.
Table 16. FLASH_BIU Settings vs. Frequency of Operation
Maximum Frequency (MHz) APC
RWSC WWSC DPFEN IPFEN
up to and including 82 MHz1 0b001 0b001
up to and including 102 MHz5 0b001 0b010
up to and including132 MHz6 0b010 0b011
0b01
0b01
0b01
0b00,
0b01, or
0b112
0b00,
0b01, or
0b112
0b00,
0b01, or
0b112
0b00,
0b01, or
0b112
0b00,
0b01, or
0b112
0b00,
0b01, or
0b112
Default Setting after Reset 0b111 0b111
0b11
0b00
1 This setting allows for 80 MHz system clock with 2% frequency modulation.
0b00
PFLIM
0b000-
0b1103
BFEN
0b0, 0b14
0b000- 0b0, 0b14
0b1103
0b000- 0b0, 0b14
0b1103
0b000
0b0
MPC5553 Microcontroller Data Sheet, Rev. 0
22
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
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