PSD4256G6V View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'PSD4256G6V' PDF : 100 Pages View PDF
PSD4256G6V
REGISTER BIT DEFINITION
All the registers of the PSD are included here, for
reference. Detailed descriptions of these registers
can be found in the following sections.
Table 7. Data-In Registers - Ports A, B, C, D, E, F, and G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Port pin 7 Port pin 6 Port pin 5 Port pin 4
Note: Bit Definitions (Read only registers):
READ Port pin status when Port is in MCU I/O input mode.
Port pin 3
Bit 2
Port pin 2
Table 8. Data-Out Registers - Ports A, B, C, D, E, F, and G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2
Note: Bit Definitions:
Latched data for output to Port pin when pin is configured in MCU I/O output mode.
Table 9. Direction Registers - Ports A, B, C, D, E, F, and G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3
Note: Bit Definitions:
Portpin <i> 0 = Port pin <i> is configured in Input mode (default).
Portpin <i> 1 = Port pin <i> is configured in Output mode.
Bit 2
Port pin 2
Table 10. Control Registers - Ports E, F, and G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3
Note: Bit Definitions:
Portpin <i> 0 = Port pin <i> is configured in MCU I/O mode (default).
Portpin <i> 1 = Port pin <i> is configured in Latched Address Out mode.
Bit 2
Port pin 2
Table 11. Drive Registers - Ports A, B, D, E, and G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3
Note: Bit Definitions:
Portpin <i> 0 = Port pin <i> is configured for CMOS Output driver (default).
Portpin <i> 1 = Port pin <i> is configured for Open Drain output driver.
Bit 2
Port pin 2
Table 12. Enable-Out Registers - Ports A, B, C, and F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3
Note: Bit Definitions (Read only registers):
Portpin <i> 0 = Port pin <i> is in tri-state driver (default).
Portpin <i> 1 = Port pin <i> is enabled.
Bit 2
Port pin 2
Bit 1
Port pin 1
Bit 1
Port pin 1
Bit 1
Port pin 1
Bit 1
Port pin 1
Bit 1
Port pin 1
Bit 1
Port pin 1
Bit 0
Port pin 0
Bit 0
Port pin 0
Bit 0
Port pin 0
Bit 0
Port pin 0
Bit 0
Port pin 0
Bit 0
Port pin 0
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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