PSD813F1AV-12J View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
PSD813F1AV-12J
STMicroelectronics
'PSD813F1AV-12J' PDF : 110 Pages View PDF
PSD813F1V
Data Byte Enable Reference
Microcontrollers have different data byte orienta-
tions. The following table shows how the PSD in-
terprets byte/word operations in different bus
WRITE configurations. Even-byte refers to loca-
tions with address A0 equal to zero and odd byte
as locations with A0 equal to one.
Table 16. Eight-Bit Data Bus
BHE
A0
X
0
X
1
D7-D0
Even Byte
Odd Byte
MCU Bus Interface Examples
Figure 23 to 26 show examples of the basic con-
nections between the PSD and some popular
MCUs. The PSD Control input pins are labeled as
to the MCU function for which they are configured.
The MCU bus interface is specified using the PS-
Dsoft Express Configuration.
The first configuration is 80C31-compatible, and
the bus interface to the PSD is identical to that
shown in Figure 23. The second and third configu-
rations have the same bus connection as shown in
Table 17., page 48. There is only one READ input
(PSEN) connected to the CNTL1 pin on the PSD.
The A16 connection to the PA0 pin allows for a
larger address input to the PSD. Configuration 4 is
shown in Figure 24., page 49. The RD signal is
connected to Cntl1 and the PSEN signal is con-
nected to the CNTL2.
80C31
Figure 23 shows the bus interface for the 80C31,
which has an 8-bit multiplexed address/data bus.
The lower address byte is multiplexed with the
data bus. The MCU control signals Program Se-
lect Enable (PSEN, CNTL2), Read Strobe (RD,
CNTL1), and Write Strobe (WR, CNTL0) may be
used for accessing the internal memory and I/O
Ports. The ALE input (pin PD0) latches the ad-
dress.
Figure 23. Interfacing the PSD with an 80C31
RESET
RESET
80C31
31
EA/VP
19 X1
18 X2
9 RESET
12
13 INT0
14
15
INT1
T0
T1
1
2
3
4
5
6
P1.0
P1.1
P1.2
P1.3
P1.4
7
P1.5
P1.6
8 P1.7
39
P0.0
P0.1
38
37
P0.2
P0.3
P0.4
36
35
P0.5
P0.6
P0.7
34
33
32
P2.0 21
P2.1 22
P2.2 23
P2.3 24
P2.4 25
P2.5
P2.6
P2.7
26
27
28
RD 17
WR 16
PSEN 29
30
ALE/P
11
TXD
RXD 10
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A11
A12
A13
A14
A15
RD
WR
PSEN
ALE
RESET
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD7-AD0
PSD
30
31
32
33
34
ADIO0
ADIO1
ADIO2
ADIO3
35 ADIO4
36
37
ADIO5
ADIO6
ADIO7
39 ADIO8
40
41
42
ADIO9
ADIO10
ADIO11
43 ADIO12
44 ADIO13
45
46
ADIO14
ADIO15
47 CNTL0 (WR)
50 CNTL1(RD)
49 CNTL2 (PSEN)
10 PD0-ALE
9 PD1
8 PD2
48
RESET
AD[ 7:0]
PA0
29
28
PA1 27
PA2
PA3
PA4
25
24
23
PA5
PA6
22
PA7 21
PB0
7
6
PB1
PB2
5
PB3
PB4
4
3
2
PB5
PB6
52
PB7 51
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
20
19
18
17
14
13
12
11
AI02880C
47/110
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