PSD813F1V-70JT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
PSD813F1V-70JT
STMicroelectronics
'PSD813F1V-70JT' PDF : 110 Pages View PDF
PSD813F1V
JTAG In-System Programming (ISP)
Port C is JTAG compliant, and can be used for In-
System Programming (ISP). You can multiplex
JTAG operations with other functions on Port C
because ISP is not performed during normal sys-
tem operation. For more information on the JTAG
Port, see the section entitled PROGRAMMING IN-
CIRCUIT USING THE JTAG SERIAL
INTERFACE, page 71.
Port Configuration Registers (PCR)
Each Port has a set of Port Configuration Regis-
ters (PCR) used for configuration. The contents of
the registers can be accessed by the MCU through
normal READ/WRITE bus cycles at the addresses
given in Table 6., page 17. The addresses in Ta-
ble 6., page 17 are the offsets in hexadecimal from
the base of the CSIOP register.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, Bit 0 in a register refers to Bit 0 of its
port. The three Port Configuration Registers
(PCR), shown in Table 22, are used for setting the
Port configurations. The default Power-up state for
each register in Table 22 is 00h.
Control Register
Any bit reset to ‘0’ in the Control Register sets the
corresponding port pin to MCU I/O Mode, and a ‘1’
sets it to Address Out Mode. The default mode is
MCU I/O. Only Ports A and B have an associated
Control Register.
Table 22. Port Configuration Registers (PCR)
Register Name
Port
MCU Access
Control
A,B
WRITE/READ
Direction
A,B,C,D
WRITE/READ
Drive Select1
A,B,C,D
WRITE/READ
Note: 1. See Table 26., page 58 for Drive Register bit definition.
57/110
Share Link: 