PSD835G2-12B81 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'PSD835G2-12B81' PDF : 110 Pages View PDF
PSD8XX Family
The
PSD835G2
Functional
Blocks
(cont.)
PSD835G2
Figure 15. Handshaking Communication Using Input Micro⇔Cells
PSD835G2
MCU- RD
MASTER MCU- WR
MCU
D[ 7:0]
CPLD
SLAVE– CS
RD
WR
SLAVE– READ
PORT A
DATA OUT
REGISTER
MCU- WR
DQ
SLAVE– WR
PORT A
INPUT
MICRO ⇔CELL
QD
MCU- RD
D [ 7:0]
PORT A
SLAVE
MCU
9.2.2.7 External Chip Select
The CPLD also provides eight chip select outputs that can be used to select external
devices. The chip selects can be routed to either Port C or Port F, depending on the pin
declaration in the PSDsoft. Each chip select (ECS0-7) consists of one product term that can
be configured active high or low.
The output enable of the pin is controlled by either the output enable product term or the
Direction Register. (See Figure 16).
Figure 16. External Chip Select
ENABLE (.OE) PT
CPLD
AND
ARRAY
ECS PT
POLARITY
BIT
ECS
TO PORT C OR F
DIRECTION
REGISTER
PORT PIN
PORT C OR PORT F
42
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