PSD913F3V-15JT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'PSD913F3V-15JT' PDF : 110 Pages View PDF
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Port D – Functionality and Structure
Port D has three I/O pins. See Figure 30 and Fig-
ure 31., page 61. This port does not support Ad-
dress Out mode, and therefore no Control
Register is required. Port D can be configured to
perform one or more of the following functions:
■ MCU I/O Mode
■ CPLD Output – External Chip Select (ECS0-
ECS2)
■ CPLD Input – direct input to the CPLD, no
Input Macrocells (IMC)
■ Slew rate – pins can be set up for fast slew
rate
Port D pins can be configured in PSDsoft Express
as input pins for other dedicated functions:
■ Address Strobe (ALE/AS, PD0)
■ CLKIN (PD1) as input to the macrocells flip-
flops and APD counter
■ PSD Chip Select Input (CSI, PD2). Driving this
signal High disables the Flash memory, SRAM
and CSIOP.
Figure 30. Port D Structure
DATA OUT
REG.
DQ
WR
ECS[ 2:0]
READ MUX
P
D
B
DATA OUT
OUTPUT
MUX
DATA IN
OUTPUT
SELECT
PORT D PIN
DIR REG.
DQ
WR
ENABLE PRODUCT
TERM (.OE)
CPLD - INPUT
AI02889
60/110
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