PSD913F3V-90MI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'PSD913F3V-90MI' PDF : 110 Pages View PDF
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode
Port Configuration
Power-On Reset
Warm Reset
Power-down Mode
MCU I/O
Input mode
Input mode
Unchanged
PLD Output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Address Out
Tri-stated
Tri-stated
Not defined
Data Port
Tri-stated
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
Tri-stated
Register
Power-On Reset
Warm Reset
Power-down Mode
PMMR0 and PMMR2
Cleared to '0'
Unchanged
Unchanged
Macrocells flip-flop status
Cleared to '0' by internal
Power-On Reset
Depends on .re and .pr
equations
Depends on .re and .pr
equations
VM Register1
Initialized, based on the
selection in PSDsoft
Configuration menu
Initialized, based on the
selection in PSDsoft
Configuration menu
Unchanged
All other registers
Cleared to '0'
Cleared to '0'
Unchanged
Note: 1. The SR_cod and PeriphMode bits in the VM Register are always cleared to '0' on Power-On Reset or Warm Reset.
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