QL5030-4TQ144C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5030-4TQ144C
QuickLogic Corporation
'QL5030-4TQ144C' PDF : 18 Pages View PDF
QL5030 QuickPCI Data Sheet
11.0 AC CHARACTERISTICS at VCC = 3.3V, TA = 25×C (K = 1.00)
To calculate delays, multiply the appropriate K factor in the “Operating Range” section by the following
numbers.
Table 6: Logic Cells
Symbol
Parameter
Propagation Delays (ns)
Fanout [a]
1
2
3
4
8
tPD
Combinatorial Delay
1.4
1.7
1.9
2.2
3.2
tSU
Setup Time
1.7
1.7
1.7
1.7
1.7
tH
Hold Time
0.0
0.0
0.0
0.0
0.0
tCLK
Clock to Q Delay
0.7
1.0
1.2
1.5
2.5
tCWHI Clock High Time
1.2
1.2
1.2
1.2
1.2
tCWLO Clock Low Time
1.2
1.2
1.2
1.2
1.2
tSET
Set Delay
1.0
1.3
1.5
1.8
2.8
tRESET Reset Delay
0.8
1.1
1.3
1.6
2.6
tSW
Set Width
1.9
1.9
1.9
1.9
1.9
tRW
Reset Width
1.8
1.8
1.8
1.8
1.8
a. These limits are derived from a representative selection of the slowest paths through the Quick-
RAM logic cell including typical net delays. Worst case delay values for specific paths should be
determined from timing analysis of your particular design.
Table 7: RAM Cell Synchronous Write Timing
Symbol
Parameter
Propagation Delays (ns)
Fanout [a]
1
2
3
4
8
tSWA WA Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
tHWA WA Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
tSWD WD Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
tHWD WD Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
tSWE WE Setup Time to WCLK
1.0
1.0
1.0
1.0
1.0
tHWE WE Hold Time to WCLK
0.0
0.0
0.0
0.0
0.0
tWCRD WCLK to RD (WA=RA) [4]
5.0
5.3
5.6
5.9
7.1
a. Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25×C.
Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as
specified in the Operating Range.
QL5030 QuickPCI Data Sheet Rev C
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