QL5032-33APQ208I View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5032-33APQ208I

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and dual Port SRAM

QuickLogic Corporation 

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QL5032 - QuickPCITM

PCI Target Interface (Continued)

Cfg_RdData[31:0]

Usr_RdData[31:0]

Cfg_CmdReg8

Cfg_CmdReg6

Cfg_LatCnt[7:0]

Usr_MstRdAd_Sel

Usr_MstWrAd_Sel

Cfg_PERR_Det

Cfg_SERR_Sig

Cfg_MstPERR_Det

Usr_TRDYN

Usr_STOPN

Usr_Devsel

Usr_Last_Cycle_D1

Usr_Rdy

Usr_Stop

Usr_Interrupt

I Data from the PCI configuration registers, required to be presented during PCI

configuration reads.

I Data from the back-end user logic (and/or DMA configuration registers),

required to be presented during PCI reads.

I Bits 6 and 8 from the Command Register in the PCI configuration space (offset

04h).

I 8-bit value of the Latency Timer in the PCI configuration space (offset 0Ch).

I Used when a target read operation should return the value set on the

Mst_RdAd[31:0] pins. This select pin saves on logic which would otherwise

need to be used to multiplex Mst_RdAd[31:0] into the Usr_RdData[31:0] bus.

When this signal is asserted, the data on Usr_RdData[31:0] is ignored.

I Used when a target read operation should return the value set on the

Mst_WrAd[31:0] pins. This select pin saves on logic which would otherwise

need to be used to multiplex Mst_WrAd[31:0] into the Usr_RdData[31:0] bus.

When this signal is asserted, the data on Usr_RdData[31:0] is ignored.

O Parity error detected on the PCI bus. When this signal is active, bit 15 of the

Status Register must be set in the PCI configuration space (offset 04h).

O System error asserted on the PCI bus. When this signal is active, the Signalled

System Error bit, bit 14 of the Status Register, must be set in the PCI

configuration space (offset 04h).

O Data parity error detected on the PCI bus by the master. When this signal is

active, bit 8 of the Status Register must be set in the PCI configuration space

(offset 04h).

O Copy of the TRDYN signal as driven by the PCI target interface.

O Copy of the STOPN signal as driven by the PCI target interface.

O Inverted copy of the DEVSELN signal as driven by the PCI target interface.

O Last transfer in a PCI transaction is occurring.

I Used to delay (add wait states to) a PCI transaction when the back end needs

additional time. Subject to PCI latency restrictions.

I Used to prematurely stop a PCI target access on the next PCI clock.

I Used to signal an interrupt on the PCI bus.

6

6

Preliminary

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