QL5064-33APB456C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5064-33APB456C
QuickLogic Corporation
'QL5064-33APB456C' PDF : 37 Pages View PDF
QL5064 QuickPCI Data Sheet
6.0 Mailbox Registers and I2O
The PCI interface contains 16 bytes of mailbox registers to support message/semaphore passing
between the programmable logic design and the PCI bus. These mailbox registers are memory mapped
to a dedicated register bank within the first 256 bytes of BAR 0. 8 bytes are provided for the FPGA to
PCI direction, and 8 bytes are also provided for the PCI to FPGA direction. Status flags and interrupts
are available for each direction as well. Figure 4 below shows the mailbox structure within the QL5064
device. Hardware controlled queues allow full I2O messaging support with a processor and local I2O
drivers.
outgoing
decode
control
63
byte 7
byte 6
byte 5
byte 4
byte 3
byte 2
byte 1
0
byte 0
interrupt
configuration
register
status
STATUS REGISTER
INTERRUPT CONTROL
status
full interrupt
empty interrupt
empty interrupt
full interrupt
status
INTERRUPT CONTROL
status
interrupt
configuration
register
63
byte 7
byte 6
STATUS REGISTER
byte 5 byte 4 byte 3 byte 2
byte 1
0
byte 0
incoming
decode
control
PCI BUS
mailbox 7
mailbox 6 mailbox 5 mailbox 4 mailbox 3 mailbox 2 mailbox 1
User Outgoing mailboxes
mailbox 0
Figure 4: Mailbox Structure
CNTL
BUS
QL5064 QuickPCI Data Sheet Rev D
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