QL5332 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5332
QuickLogic Corporation
'QL5332' PDF : 25 Pages View PDF
QL5332 QuickPCI Data Sheet Rev. C
Table 11: RAM Cell Synchronous Write Timing
Symbol
Parameter
Propagation Delays (ns)
Fanouta
1
2
3
4
8
WA setup time to WCLK: time the WRITE
tSWA ADDRESS must be stable before the active edge of 1.0
1.0
1.0
1.0
1.0
the WRITE CLOCK
WA hold time to WCLK: time the WRITE ADDRESS
tHWA must be stable after the active edge of the WRITE
0.0
0.0
0.0
0.0
0.0
CLOCK
WD setup time to WCLK: time the WRITE DATA
tSWD must be stable before the active edge of the WRITE 1.0
1.0
1.0
1.0
1.0
CLOCK
tHWD
WD hold time to WCLK: time the WRITE DATA must
be stable after the active edge of the WRITE CLOCK
0.0
0.0
0.0
0.0
0.0
WE setup time to WCLK: time the WRITE ENABLE
tSWE must be stable before the active edge of the WRITE 1.0
1.0
1.0
1.0
1.0
CLOCK
WE hold time to WCLK: time the WRITE ENABLE
tHWE must be stable after the active edge of the WRITE
0.0
0.0
0.0
0.0
0.0
CLOCK
WCLK to RD (WA = RA): time between the active
tWCRD WRITE CLOCK edge and the time when the data is 5.0
5.3
5.6
5.9
7.1
available at RD
a. Stated timing for worst case Propagation Delay over process variation at VCC=3.3 V and TA=25×C. Multiply by the
appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
Table 12: RAM Cell Synchronous Read Timing
Symbol
Parameter
Propagation Delays (ns)
Fanout
1
2
3
4
8
tSRA
RA setup time to RCLK: time the READ ADDRESS must
be stable before the active edge of the READ CLOCK
1.0
1.0
1.0
1.0
1.0
tHRA
RA hold time to RCLK: time the READ ADDRESS must
be stable after the active edge of the READ CLOCK
0.0
0.0
0.0
0.0
0.0
tSRE
RE setup time to RCLK: time the READ ENABLE must be
stable before the active edge of the READ CLOCK
1.0
1.0
1.0
1.0
1.0
tHRE
RE hold time to RCLK: time the READ ENABLE must be
stable after the active edge of the READ CLOCK
0.0
0.0
0.0
0.0
0.0
tRCRD
RCLK to RD: time between the active READ CLOCK
edge and the time when the data is available at RDa
4.0
4.3
4.6
4.9
6.1
a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including
typical net delays. Worst case delay values for specific paths should be determined from timing analysis of a particular
design.
© 2004 QuickLogic Corporation
www.quicklogic.com
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