QL5632-33B-PQ208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5632-33B-PQ208C
QuickLogic Corporation
'QL5632-33B-PQ208C' PDF : 39 Pages View PDF
QL5632 Enhanced QuickPCI Device Data Sheet Rev. C
Signal
Mst_Rd_Term_Sel
Mst_One_Read
Mst_Two_Reads
Mst_RdData_Valid
Mst_RdBurst_Done
Flush_FIFO
Mst_LatCntEn
Mst_Xfer_D1
Mst_Last_Cycle
Mst_REQN
Mst_IRDYN
Mst_Tabort_Det
Mst_TTO_Det
Table 10: PCI Master Interface
Type
Description
Master Read termination mode select when Mst_BE_Sel is high
When both Mst_BE_Sel and Mst_Rd_Term_Sel are high, master Read
I
termination happens when the internal FIFO is empty, and Mst_Two_Reads
and Mst_One_Read are ignored. When either signal is low, Mst_Two_Reads
and Mst_One_Read are used to signal end of master Read. Should be held
constant throughout the transaction.
I
This signals to the PCI32 core that only one data transfer remains to be read
in the burst Read.
I
Two data transfers remain to be read in the burst Read It is not used
for single-data-phase master read transactions.
Master Read data valid on Usr_Addr_WrData[31:0] This serves as
O the PUSH control for the external FIFO (in FPGA region) that receives data
from the PCI32 core.
O Master Read transaction is completed Active for only one clock cycle.
I
Internal FIFO flush FIFO flushed immediately after it is active
(synchronized with PCI clock).
Enable Latency Counter Set to 0 to ignore the Latency Timer in the PCI
I configuration space (offset 0Ch).
For full PCI compliance, this port should be always set to 1.
O
Data was transferred on the previous PCI clock Useful for updating
DMA transfer counts on DMA Read operations
O Active during the last data transfer of a master transaction
O
Copy of the PCI REQN signal generated by QL5632 as PCI master
Not usually used in the back-end design.
Copy of the PCI IRDYN signal generated by QL5632 as PCI
O master Valid only when QL5 × 33 is the PCI master. Kept low otherwise.
Not usually used in the back-end design.
O
Target abort detected during master transaction This is normally an
error condition to be handled in the DMA controller.
O
Target timeout detected (no response from target) This is normally
an error condition to be handled in the DMA controller.
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