QL5632 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5632
QuickLogic Corporation
'QL5632' PDF : 39 Pages View PDF
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The AC characteristics are calculated at 2.5 V, TA = 25°C (K = 0.74). To calculate delays,
multiply the appropriate K factor in 7DEOH by the numbers presented in 7DEOH through
7DEOH
7DEOH /RJLF &HOOV
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/RJLF &HOOV
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tPD
Combinatorial Delay of the longest path: time taken by the combinatorial
circuit to output
Setup time: time the synchronous input of the flip flop must be stable before the
tSU
active
clock edge
Hold time: time the synchronous input of the flip flop must be stable after the
tHL
active
clock edge
tCO
Clock to out delay: the amount of time taken by the flip flop to output after the
active clock edge.
tCWHI
tCWLO
tSET
Clock High Time: required minimum time the clock stays high
Clock Low Time: required minimum time that the clock stays low
Set Delay: time between when the flip flop is ”set” (high) and when the output is
consequently “set” (high)
tRESET
Reset Delay: time between when the flip flop is ”reset” (low) and when the output
is consequently “reset” (low)
tSW
Set Width: time that the SET signal remains high/low
tRW
Reset Width: time that the RESET signal remains high/low
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0LQ 0D[
- 0.257
0.22
-
0
-
- 0.255
0.46
-
0.46
-
-
0.18
-
0.09
0.3
-
0.3
-
SET
D
Q
CLK
RESET
Figure 9: Logic Cell
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Preliminary
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