QL5632 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5632
QuickLogic Corporation
'QL5632' PDF : 39 Pages View PDF
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The internal signals used to interface with the PCI controller in the QL5632 are listed in
7DEOH along with a description of each signal. The direction of the signal indicates if the
signal is an input provided by the local interface (I) or an output provided by the PCI controller
(O).
NOTE: Signals that end with the character ‘N’ should be considered active-low (for example,
Mst_IRDYN).
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PCI_cmd[3:0]
mst_burst_req
mst_wrAd[31:0]
mst_rdAd[31:0]
Mst_WrData[31:0]
Mst_BE[3:0]
Mst_WrData_Valid
Mst_WrData_Rdy
Mst_BE_Sel
Mst_WrBurst_Done
Mst_Rd_Term_Sel
Mst_One_Read
Mst_Two_Reads
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PCI command to be used for the master transaction This signal must remain unchanged
throughout the period when Mst_Burst_Req is active. PCI commands considered as reads include
I
Interrupt Acknowledge, I/O Read, Memory Read, Configuration Read, Memory Read Multiple,
Memory Read Line. PCI commands considered as writes include Special Cycle, I/O Write, Memory
Write, Configuration Write, Memory Write and Invalidate. Users should make sure that only valid
PCI commands are supplied.
Request use of the PCI bus When this signal is active, the core requests the PCI bus and then
I
generates a master transaction. This signal should be held active until all requested data are
transferred on the PCI bus and deactivated in the 2nd clock cycle following the last data transfer on
PCI (to avoid being considered as requesting a new transaction).
Address for master DMA writes This address must be treated as valid from the beginning of a
I DMA Write until the DMA Write operation is complete. It should be incremented by 4 bytes each
time data is transferred on the PCI bus.
Address for master DMA reads This address must be treated as valid from the beginning of a
I DMA read until the DMA Read operation is complete. It should be incremented by 4 bytes each time
data is transferred on the PCI bus.
I Data for master DMA Writes (to PCI bus)
I Byte enables for master DMA Reads and writes Active-low.
I
Data and byte enable valid on Mst_WrData[31:0] (for master Write only) and
Mst_BE[3:0] (for both master Read and Write)
Data receive acknowledge for Mst_WrData[31:0] (for master Write only) and
O
Mst_BE[3:0] (for both) This serves as the PUSH control for the internal FIFO and the POP
control for the external FIFO (in FPGA region) which provides data and byte enables to the PCI32
core.
Byte enable select for master transactions When low, Mst_BE[3:0] should remain constant
I
throughout the entire transfer (when Mst_Burst_Req is active) and it is used for every data phase of
the master transaction. When high, Mst_BE[3:0] pushed into internal FIFO (along with data in case
of master Write) is used. Should be held constant throughout the transaction.
O Master Write transaction is completed Active for only one clock cycle.
Master Read termination mode select when Mst_BE_Sel is high When both Mst_BE_Sel
and Mst_Rd_Term_Sel are high, master Read termination happens when the internal FIFO is
I empty, and Mst_Two_Reads and Mst_One_Read are ignored. When either signal is low,
Mst_Two_Reads and Mst_One_Read are used to signal end of master Read. Should be held constant
throughout the transaction.
I This signals to the PCI32 core that only one data transfer remains to be read in the burst Read.
I
Two data transfers remain to be read in the burst Read It is not used for single-data-phase
master read transactions.
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