QL5632 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5632
QuickLogic Corporation
'QL5632' PDF : 34 Pages View PDF
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PCI_clock
PCI_reset
PCI_IRDYN_D1
PCI_FRAMEN_D1
PCI_DEVSELN_D1
PCI_TRDYN_D1
PCI_STOPN_D1
PCI_IDSEL_D1
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PCI clock.
O
PCI reset signal.
O Copy of the IRDYN signal from the PCI bus, delayed by one clock.
O Copy of the FRAMEN signal from the PCI bus, delayed by one clock.
O Copy of the DEVSELN signal from the PCI bus, delayed by one clock.
O Copy of the TRDYN signal from the PCI bus, delayed by one clock.
O Copy of the STOPN signal from the PCI bus, delayed by one clock.
O Copy of the IDSEL signal from the PCI bus, delayed by one clock.
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The QL5632 device has eighteen 2,304-bit RAM modules, for a total of 41,472 RAM bits.
Using two “mode” pins, designers can configure each module into 128 × 18, 256 × 9, 512
× 4, or 1024 × 2 blocks (see )LJXUH ). The blocks are also easily cascadable to increase their
effective width or depth.
The RAM modules are “dual-ported” with completely independent Read and Write ports and
separate Read and Write clocks. The Read ports support asynchronous and synchronous
operation, while the Write ports support synchronous operation. Each port has 18 data lines
and 10 address lines, allowing word lengths of up to 18 bits and address spaces of up to
1,024 words. Depending on the mode selected, however, some higher order data or address
lines may not be used.
The Write Enable (WE) line acts as a clock enable for synchronous Write operation. The Read
Enable (RE) acts as a clock enable for synchronous Read operation (ASYNCRD input low),
or as a flow-through enable for asynchronous Read operation (ASYNCRD input high).
Designers can cascade multiple RAM modules to increase the depth or width allowed in
single modules by connecting corresponding address lines together and dividing the words
between modules. This approach allows up to 1,024-deep configurations as large as 44 bits
wide in the QL5632 device.
A similar technique can be used to create depths greater than 1,024 words. In this case,
address signals higher than the eighth bit are encoded onto the write enable (WE) input for
Write operations. The Read data outputs are multiplexed together using encoded higher
Read address bits for the multiplexer SELECT signals.
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