QL5732-33BPS484C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5732-33BPS484C
QuickLogic Corporation
'QL5732-33BPS484C' PDF : 41 Pages View PDF
QL5732 Enhanced QuickPCI Device Data Sheet Rev. E
NOTE: "HF" stands for "high frequency" and "LF" stands for "low frequency."
PLL Model
PLL_HF
PLL_LF
PLL_MULT2HF
PLL_MULT2LF
PLL_DIV2HF
PLL_DIV2LF
PLL_MULT4
PLL_DIV4
Table 5: PLL Mode Frequencies
Output
Frequency
Input Frequency Range
Same as input
66 MHz–150 MHz
Same as input
25 MHz–133 MHz
2x
50 MHz–125 MHz
2x
16 MHz–50 MHz
1/2x
100 MHz–250 MHz
1/2x
50 MHz–100 MHz
4x
16 MHz–40 MHz
1/4x
100 MHz–300 MHz
Output Frequency Range
66 MHz–150 MHz
25 MHz–133 MHz
100 MHz–250 MHz
32 MHz–100 MHz
50 MHz–125 MHz
25 MHz–50 MHz
64 MHz–160 MHz
25 MHz–75 MHz
NOTE: The input frequency can range from 16 MHz to 300 MHz, while output frequency
ranges from 25 MHz to 250 MHz. When you add PLLs to your top-level design, be sure
that the PLL mode matches your desired input and output frequencies.
PLL Signals
Table 6 summarizes the key signals in QuickLogic's PLLs.
Table 6: PLL Signals
Signal Name
Description
PLLCLK_IN Input clock signal
PLL_RESET
Active High Reset If PLL_RESET is asserted, then CLKNET_OUT and
PLLPAD_OUT are reset to 0. This signal must be asserted and then released
in order for the LOCK_DETECT to work.
ONn_OFFCHIP
PLL output This signal selects whether the PLL will drive the internal clock
network or be used off-chip. This is a static signal, not a dynamic signal.
Tied to GND = outgoing signal drives internal gates.
Tied to VCC = outgoing signal used off-chip.
Out to internal gates This signal bypasses the PLL logic before driving the
CLKNET_OUT internal gates. Note that this signal cannot be used in the same quadrant where
the PLL signal is used (PLLCLK_OUT).
PLLCLK_OUT
Out from PLL to internal gates This signal can drive the internal gates after
going through the PLL. For this to work, ONn_OFFCHIP must be tied to GND.
PLLPAD_OUT
Out to off-chip This outgoing signal is used off-chip. For this to work,
ONn_OFFCHIP signal must be tied to VCC.
Active High Lock detection signal NOTE: For simulation purposes, this
LOCK_DETECT signal gets asserted after 10 clock cycles. However, it can take a maximum of
200 clock cycles to sync with the input clock upon release of the RESET signal.
NOTE: Because PLLCLK_IN and PLL_RESET signals have INPAD, and PLLPAD_OUT has
OUTPAD, you do not have to add additional pads to your design.
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