QL6250-E-7PT280I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
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'QL6250-E-7PT280I' PDF : 37 Pages View PDF
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All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance) internally
using the Configuration Editor. This option is given in the bottom-right corner of the placement
window. To use the Placement Editor, choose Constraint > Fix Placement in the Option pull-
down menu of SpDE.
The rest of the pins should be terminated at the board level in the manner presented in 7DEOH .
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PLLOUT<x>a
IOCTRL<y>b
CLK/PLLIN<x>
PLLRST<x>
INREF<y>
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Unused PLL output pins must be connected to either VCC or GND so that their associated
input buffer never floats. Utilized PLL output pins that route the PLL clock outside of the
chip should not be tied to either VCC or GND.
Any unused pins of this type must be connected to either VCC or GND.
Any unused clock pins should be connected to VCC or GND.
If a PLL module is not used, then the associated PLLRST<x> must be connected to VCC;
under normal operation, use it as needed.
If an I/O bank does not require the use of INREF signal the pin should be connected to
GND.
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