QL6325-E-6PQ208M View Datasheet(PDF) - QuickLogic Corporation
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MFG CO.
'QL6325-E-6PQ208M' PDF : 56 Pages View PDF
QL6325E Eclipse-E Data Sheet Rev. F
AC Characteristics*
*At VCC = 2.5 V, TA = 25°C, Worst Case Corner, Speed Grade = -6 (K = 1.01).
The AC Specifications are provided from Table 13 to Table 22. Logic cell diagrams and waveforms are
provided from Figure 25 to Figure 38.
Figure 25: Eclipse-E Logic Cell
Symbol
tPD
tSU
tHL
tCO
tCWHI
tCWLO
tSET
tRESET
tSW
tRW
Table 13: Logic Cell Delays
Parameter
Combinatorial Delay of the longest path: time taken by the combinatorial circuit
to output
Setup time: time the synchronous input of the flip-flop must be stable before the
active clock edge
Hold time: time the synchronous input of the flip-flop must be stable after the
active clock edge
Clock-to-out delay: the amount of time taken by the flip-flop to output after the
active clock edge.
Clock High Time: required minimum time the clock stays high
Clock Low Time: required minimum time that the clock stays low
Set Delay: time between when the flip-flop is ”set” (high)
and when the output is consequently “set” (high)
Reset Delay: time between when the flip-flop is ”reset” (low) and when the
output is consequently “reset” (low)
Set Width: time that the SET signal must remain high/low
Reset Width: time that the RESET signal must remain high/low
Value
Min
Max
0.28 ns 0.98 ns
0.10 ns 0.25 ns
0 ns
0 ns
0.22 ns
0.46 ns
0.46 ns
0.69 ns
0.52 ns
0.46 ns
0.46 ns
0.69 ns
1.09 ns
0.3 ns
0.3 ns
1.09 ns
0.3 ns
0.3 ns
© 2005 QuickLogic Corporation
www.quicklogic.com
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