QL6325-E-8PT280I View Datasheet(PDF) - QuickLogic Corporation
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Description
MFG CO.
'QL6325-E-8PT280I' PDF : 56 Pages View PDF
QL6325E Eclipse-E Data Sheet Rev. F
Clock Networks
Global Clocks
There are a maximum of eight global clock networks in each Eclipse-E device. Global clocks can drive logic
cells and I/O registers, ECUs, and RAM blocks in the device. All global clocks have access to a Quad Net (local
clock network) connection with a programmable connection to the logic cell’s register clock input.
Figure 10: Global Clock Architecture
Quad Net
Global Clock Net
CLK Pin
Quad-Net Network
There are five Quad-Net local clock networks in each quadrant for a total of 20 in a device. Each Quad-Net is
local to a quadrant. Before driving the columns clock buffers, the quad-net is driven by the output of a mux
which selects between the CLK pin input and an internally generated clock source (see Figure 11).
Figure 11: Global Clock Structure
Internally generated clock, or
clock from general routing network
Global Clock
(CLK) Input
Quad-Net Clock Network
FF
12
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Global Clock Buffer
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