QL6325-E-8PT280I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL6325-E-8PT280I' PDF : 56 Pages View PDF
QL6325E Eclipse-E Data Sheet Rev. F
Figure 29: Eclipse-E Global Clock Structure
Quad net
Clock Segment
tPGCK
tBGCK
tDPD
tGSKEW
tDSKEW
Table 14: Eclipse-E Tree Clock Delay
Parameter
Min
Global clock pin delay to quad net
-
Global clock tree delay (quad net to flip-flop)
-
Dedicated clock pad
-
Global delay clock skew
-
Dedicated clock skew
-
Value
Max
1.92 ns
0.28 ns
1.7 ns
0.1 ns
0.05 ns
NOTE: When using a PLL, tPGCK and tBGCK are effectively zero due to delay adjustment by Phase Locked
Loop feedback path.
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www.quicklogic.com
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